The present invention relates to a ferroelectric-type nonvolatile semiconductor memory (so-called FERAM).
In recent years, studies are actively made with regard to a mass-storage ferroelectric-type nonvolatile semiconductor memory. A ferroelectric-type nonvolatile semiconductor memory (to be sometimes abbreviated as “nonvolatile memory” hereinafter) permits fast access and is nonvolatile, and it is small in size and consumes low-level electric power. Further, the nonvolatile memory has high impact-resistant, and it is expected to be used as a main memory in various electronic devices having file storage and resume functions, such as a portable computer, a cellular phone and a game machine, or to be used as a recording medium for recording voices and video images.
The above nonvolatile memory is a fast rewritable nonvolatile memory according to a method in which fast polarization inversion of a ferroelectric thin film and residual polarization thereof are used, and a change in an accumulated charge amount in a memory cell (capacitor member) having a ferroelectric layer is detected. In principle, it comprises the memory cell (capacitor member) and a transistor for selection (transistor for switching). The memory cell (capacitor member) comprises, for example, a lower electrode, an upper electrode and a ferroelectric layer interposed between them. Reading-out and writing of data in the above nonvolatile memory is carried out by application of a P-E hysteresis loop of a ferroelectric material shown in FIG. 26. That is, when an external electric field is applied to the ferroelectric layer and then removed, the ferroelectric layer exhibits residual polarization. The residual polarization of the ferroelectric layer comes to be +Pr when an external electric field in the plus direction is applied, and it comes to be −Pr when an external electric field in the minus direction is applied. In this case, a case where the residual polarization is in a +Pr state (see “D” in FIG. 26) is taken as “0”, and a case where the residual polarization is in a −Pr state (see “A” in FIG. 26) is taken as “1”.
For discriminating states of “1” and “0”, an external electric field, for example, in the plus direction is applied to the ferroelectric layer, whereby the polarization of the ferroelectric layer comes to be in a “C” state in FIG. 26. When the data is “0”, the polarization state of the ferroelectric layer changes from “D” to “C”. When the data is “1”, the polarization state of the ferroelectric layer changes from “A” to “C” through “B”. When the data is “0”, no polarization inversion takes place in the ferroelectric layer. When the data is “1”, polarization inversion takes place in the ferroelectric layer. As a result, there is caused a difference in the accumulated charge amount in the memory cell. The transistor for selection in a selected nonvolatile memory is turned on, whereby the accumulated charge is detected as a signal current. When the external electric field is changed to 0 after the data is read out, the polarization state of the ferroelectric layer comes into a “D” state in FIG. 26 both when the data is “0” and when the data is “1”. That is, when the data is read out, the data “1” is once destroyed. When the data is “1”, therefore, an external electric field in the minus direction is applied, so that the polarization state is brought into “A” state through “D” and “E” to re-write data “1”.
The structure and the operation of a currently mainstream nonvolatile memory are proposed by S. Sheffiled et al in U.S. Pat. No. 4,873,664. This nonvolatile memory comprises, for example, transistors for selection TR11 and TR12 and memory cells (capacitor member) FC11 and FC12 as FIG. 27 shows its circuit diagram. In FIG. 27, each nonvolatile memory is surrounded by a dotted line.
Concerning two-digit or three-digit subscripts, for example, a subscript “11” is a subscript that should be shown as “1,1”, and for example, a subscript “111” is a subscript that should be shown as “1,1,1”. For simplified showing, the subscripts are shown as two-digit or three-digit subscripts. Further, a subscript “M” is used to show, for example, all of a plurality of memory cells or plate lines, and a subscript “m” is used to show, for example, individuals of a plurality of memory cells or plate lines. A subscript “N” is used to show, for example, all of transistors for selection or sub-memory units, and a subscript “n” is used to show, for example, individuals of the transistors for selection or sub-memory units.
Complement data is written into each memory cell, and the memory cells store 1 bit. In FIG. 27, symbol “WL” stands for a word line, symbol “BL” stands for a bit line, and symbol “PL” stands for a plate line. When one nonvolatile memory is taken, a word line WL1 is connected to a word line decoder/driver WD. Bit lines BL1 and BL2 are connected to a differential sense amplifier SA. A plate line PL1 is connected to a plate line decoder/driver PD.
When stored data is read out from the thus-structured nonvolatile memory, the word line WL1 is selected and the plate line PL1 is driven. In this case, complement data appears in a pair of the bit lines BL1 and BL2 as voltages (bit line voltages) from a pair of the memory cells FC11 and FC12 through the transistors for selection TR11 and TR12. The voltages (bit line voltages) in a pair of the bit lines BL1 and BL2 are detected with the sense amplifier SA.
One nonvolatile memory occupies a region surrounded by the word line WL1 and a pair of the bit lines BL1 and BL2. If word lines and bit lines are arranged at a smallest pitch, therefore, the smallest area that one nonvolatile memory can have is 8F2 when the minimum processable dimension is F. The thus-structured nonvolatile memory therefore has the smallest area of 8F2. However, two transistors for selection and two memory cells are required for constituting one nonvolatile memory. Further, it is required to arrange the plate lines at the same pitch as that at which the word lines are arranged. It is therefore almost impossible to arrange the nonvolatile memories at the minimum pitch, and in reality, the area that one nonvolatile memory occupies comes to be much greater than 8F2.
Moreover, it is also required to arrange the word line decoder/drivers WD and the plate line decoder/drivers PD at a pitch equal to a pitch at which the nonvolatile memories are arranged. In other words, two decoder/drivers are required for selecting one row-address. It is therefore difficult to layout peripheral circuits, and the area that the peripheral circuits occupy comes to be large.
One of means for decreasing the area of the nonvolatile memory is disclosed in JP-A-9-121032. As shown in an equivalent circuit of FIG. 28, the nonvolatile memory disclosed in the above laid-open Patent Publication comprises a plurality of memory cells MC1M (for example, M=4) and a plurality of memory cells MC2M. The memory cells MC1M and the memory cells MC2M form pairs. Ends of the memory cells MC1M are connected to one end of the transistor for selection TR1 in parallel, and ends of the memory cells MC2M are connected to one end of the transistor for selection TR2 in parallel. The other ends of the transistors for selection TR1 and TR2 are connected to bit lines BL1 and BL2, respectively. The bit lines BL1 and BL2 forming a pair are connected to a differential sense amplifier SA. The other ends of the memory cells MC1m and MC2m (m=1, 2 . . . M) are connected to a plate line PLm, and the plate line PLm is connected to a plate line decoder/driver PD. A word line WL is connected to a word line decoder/driver WD.
Complement data is stored in a pair of the memory cells MC1m and MC2m (m=1, 2 . . . M). For reading-out of data stored, for example, in the memory cells MC1m and MC2m (wherein m is one of 1, 2, 3 and 4), the word line WL is selected, and in a state where a voltage of (½) Vcc is applied to the plate line PLj (m≠j), the plate line PLm is driven. The above Vcc is, for example, a power source voltage. By the above operation, the complement data appears in a pair of the bit lines BL1 and BL2 as voltages (bit line voltages) from a pair of the memory cells MC1m and MC2m through the transistors for selection TR1 and TR2. And, the differential sense amplifier SA detects the voltages (bit line voltages) in a pair of the bit lines BL1 and BL2.
A pair of the transistors for selection TR1 and TR2 in the nonvolatile memory occupy a region surrounded by the word lines WL and a pair of the bit lines BL1 and BL2. If the word lines and the bit lines are arranged at the smallest pitch, therefore, a pair of the transistors for selection TR1 and TR2 in the nonvolatile memory have a minimum area of 8F2. Since, however, a pair of the transistors for selection TR1 and TR2 are shared by M sets of pairs of the memory cells MC1m and MC2m (m=1, 2 . . . M), the number of the transistors for selection TR1 and TR2 per bit can be decreased, and the layout of the word lines WL is moderate, so that the nonvolatile memory can be easily decreased in size. Further, with regard to peripheral circuits, M bits can be selected with one word line decoder/driver WD and the plate line decoder/drivers PD that are M in number. When the above constitution is employed, therefore, a layout in which the cell area is close to 8F2 can be attained, and a chip size almost equal to a DRAM can be attained.
For increasing the capacity of the nonvolatile memory, it is essential to make finer memory cells, and it is also inevitably required to decrease the area of the ferroelectric layer. However, with a decrease in the area of the ferroelectric layer, naturally, the amount of an accumulated charge decreases.
As measures to take to solve the problem that the amount of an accumulated charge decreases, it is conceivable to stack the memory cells FC11 and FC12 or the memory cells MC1M and MC2M through an insulating layer in the nonvolatile memory shown in FIG. 27 or 28.
When the memory cells are stacked through the insulating layer as described above, the thermal history of the ferroelectric layer constituting the memory cell FC11 or the memory cell MC1M comes to differ from the thermal history of the ferroelectric layer constituting the memory cell FC12 or the memory cell MC2M. That is, for forming the ferroelectric layer, it is required to heat-treat a ferroelectric thin film for crystallization thereof after the formation of the ferroelectric thin film. Therefore, a ferroelectric layer constituting a memory cell positioned in a lower layer (stage) is crystallized to a greater extent than a ferroelectric layer constituting a memory cell positioned in an upper layer (stage), which causes a difference in polarization properties between the memory cell positioned in a lower layer and the memory cell positioned in an upper layer. Even if the memory cell positioned in a lower layer and the memory cell positioned in an upper layer store the same data, therefore, there is caused a difference between potentials that appear in the bit lines. The above phenomenon causes an operation margin to decrease, and in a worst case, an error is made in reading-out of data, and the nonvolatile memory is degraded in reliability.